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Processor Architectures
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Course Outline
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Performance Measures
Contents
Hardware Model
Subsections
Processor Architectures
Random logic
Microprogramming
State machines
Memory Hierarchy
Instruction Set Architectures
Register and Instruction Set Design
Register Design
Instruction set design
Pipelines
Instruction Level Parallelism
Virtual Memory
Shared Memory
Bus architectures (ISA, PCI, RAMBUS, DDR)
Exception Handling
IO subsystem and DMA
Darius Burschka 2002-01-20
